1. Field of the Invention
The present invention relates to a matched filter circuit used for synchronization establishment processing etc. of the spread spectrum communication as well as to a correlation calculation method therefor.
2. Description of the Related Art
In recent years, in mobile communication systems, the spread spectrum communication capable of high-speed and high-quality data communication, in particular, CDMA (code division multiple access), has become a mainstream technology. Various techniques (e.g., Japanese Patent No. 3,322,246) have been developed to construct newest mobile communication systems of this communication scheme and to solve fundamental problems of the mobile communication such as fading.
In general, CDMA base station systems incorporate a large number of large-scale reception circuits to serve for a large number of users. This leads to problems that the system cost increases with the circuit scale and the heat generation increases with the power consumption. On the other hand, mobile terminals have a problem that increase in circuit scale shortens the battery driving time.
Therefore, in both of base station systems and mobile terminals, it is strongly desired to reduce the circuit scale of reception systems or efficiently use limited circuit resources. Among such issues to be addressed, increase in functionality and reduction in power consumption are urgent issues to be attained in matched filters that are used in mobile terminals and base station reception systems.
FIG. 23 is a block diagram showing the configuration of the main part of a general CDMA reception apparatus. As shown in FIG. 23, the CDMA reception apparatus is equipped with a reception antenna 2301, a radio-frequency signal processing unit 2302 for performing prescribed filtering and amplification, an A/D converter 2303, a demodulator 2304, a decoder 2305, a codec unit 2306 for converting a decoded signal into a voice, and a matched filter 2307. The matched filter 2307 performs a correlation calculation on a spread spectrum reception signal and outputs a correlation result.
Matched filters, which are used in reception units of base station systems and mobile terminal systems in the above-described manner, output data (a delay profile) indicating to what degree data the system is about to receive will delay from reference timing. Timing information is generated on the basis of the delay profile and RAKE reception is performed.
In general, a baseband signal processing unit of a transmission unit of a CDMA mobile communication system processes data to be sent with a chiprate (i.e., spreading code rate) as a minimum unit. On the other hand, on the reception side, to increase the timing accuracy, the timing accuracy of a delay profile that is generated by the matched filter of a baseband processing unit of a reception unit is set higher than that of a one-chip interval by using an oversampling technique.
More specifically, an A/D converter that is provided immediately upstream of the matched filter generates data through 4-fold, 2-fold, or 1-fold oversampling that depends on necessary timing accuracy. The generated data is input to the matched filter and subjected to a calculation there. The matched filter also operates in accordance with the oversampling setting number.
The number of taps of the matched filter affects the circuit scale to a large extent. Therefore, in conventional matched filters, to reduce the circuit scale, 1-symbol integration is performed time-divisionally. For example, a matched filter circuit that performs 1-symbol integration in four divisional intervals incorporates a RAM for decreasing the number of taps to ¼ of a case that 1-symbol integration is performed at once and for performing cumulative addition on a ¼-symbol basis.
FIG. 1 is a block diagram showing the configuration of a conventional 1-symbol integration, 4-time-divisional matched filter circuit. As shown in FIG. 1, the matched filter circuit 100 is composed of a data shift register unit 101, a complex multiplication unit 102, a code shift register unit 103, a cumulative addition unit 104, and a RAM unit 105.
The data shift register unit 101 stores and shifts data of two systems (i.e., I and Q channels), the complex multiplication unit 102 despreads the data of the two systems (i.e., I and Q channels) by complex multiplication, and the code shift register unit 103 shifts and stores replica codes of the two systems (i.e., I and Q channels) that are necessary for the despreading. The cumulative addition unit 104 adds up despread correlation data of the respective chips and cumulatively adds results of 1-symbol integration, 4-time-divisional processing, and the RAM unit 105 stores a result of the 1-symbol integration, 4-time-divisional processing.
Although the data shift register unit 101, the complex multiplication unit 102, the code shift register unit 103, the cumulative addition unit 104, and the RAM unit 105 process data of the two systems (i.e., I and Q channels), only the processing for one channel will be described below to simplify the description.
It is assumed that one symbol consists of 256 chips, the number of taps is equal to 64 (a 1-symbol integration time is divided into four intervals), and the oversampling setting number is 4, 2, or 1. The sampling phases of data that are input to the matched filter circuit 100 are denoted by characters A, B, C, and D in the case of 4-fold oversampling setting, by characters A and C in the case of 2-fold oversampling setting, and by character A in the case of 1-fold oversampling setting.
The data shift register unit 101 incorporates 64 tap register units 106 that correspond to the respective taps and are connected to each other in a shift register structure. Outputs of the respective tap registers 106 serve as outputs of the respective taps of the data shift register 101. Each tap register unit 106 has a shift register structure consisting of four registers, four being the maximum oversampling setting number.
FIG. 2 is a timing chart outlining the processing and a search window width of the conventional 1-symbol integration, 4-time-divisional matched filter circuit 100. In FIG. 2, character A denotes timing of a reception signal portion at the head of a search window that comes earliest among reception signal portions to be subjected to the despreading. Character B denotes replica codes that are necessary for despreading the reception signal and that are arranged on the time axis so as to correspond to the reception signal portion at the head of the search window.
Characters C, D, E, F, G, H, I, and J denote data processing units in a state that a one-round sequence of data to be received has been captured by the 1-symbol integration, 4-time-divisional matched filter circuit 100. Each data processing unit has a ¼-symbol length. Therefore, to generate a delay profile by processing a 1-symbol portion of the reception signal, it is necessary to perform time-divisional processing four times (C, D, E, and F).
Processing of one time that is performed on ¼-symbol reception data by the 1-symbol integration, 4-time-divisional matched filter circuit 100 will be described below together with details of replica codes that are necessary for the processing.
To generate delay profile data for reception data in a reception signal interval a, first, replica codes to be used for despreading are input to the code shift register unit 103 of the matched filter circuit 100 by timing K. The replica codes are serial/parallel-converted at timing K and resulting codes are held until timing L by code holding register circuits of all taps of each tap group. Fixed replica codes are output to all taps of the complex multiplication unit 102.
A ¼-symbol delay profile M is calculated by shifting the reception data in the data shift register unit 101 until timing L in this state. Likewise, ¼-symbol delay profiles N, O, and P are calculated. A 1-symbol delay profile S obtained by cumulative addition is output from timing Q to timing R.
An important thing is that since the length of a reception signal interval that can be set at each moment in the data shift register unit 101 in the case of 4-fold, 2-fold, or 1-fold oversampling setting is equal to the ¼-symbol length, it is necessary to set codes for a reception signal portion in the next interval b and calculates a delay profile N immediately after calculation of a delay profile M of the reception signal interval a (C).
Therefore, in the conventional 1-symbol integration, 4-time-divisional matched filter circuit 100, the search window width becomes a ¼-symbol length when any of 4-fold, 2-fold, and 1-fold oversampling is set.
FIG. 3 is a timing chart showing a control signal, output signals TAPD0 to TAPD63 of the data shift register unit 101, and an output S of the cumulative addition unit 104 as a partial integration result of the conventional 1-symbol integration, 4-time-divisional matched filter circuit 100 of FIG. 1 in a case that 4-fold oversampling is set.
Input data having sampling phases A0, B0, C0, D0, A1, B1, C1, D1, . . . are captured in this order by the data shift register unit 101 in synchronism with respective clock pulses that are input to the data shift register unit 101, and the data are shifted.
As a result of the sequential shifts in the data shift register unit 101, an integration result for the sampling phases A0 to A63 is output as an output SA0 (output S) at timing of clock edge No. 253. An integration result for the sampling phases B0 to B63 is output as an output SB0 at timing of clock edge No. 254. An integration result for the sampling phases C0 to C63 is output as an output SC0 at timing of clock edge No. 255. An integration result for the sampling phases D0 to D63 is output as an output SD0 at timing of clock edge No. 256.
FIG. 4 is a timing chart showing a control signal, output signals TAPD0 to TAPD63 of the data shift register unit 101, and an output S of the cumulative addition unit 104 as a partial integration result of the conventional 1-symbol integration, 4-time-divisional matched filter circuit 100 of FIG. 1 in a case that 2-fold oversampling is set.
Input data having sampling phases A0, C0, A1, C1, A2, C2, A3, C3, . . . are captured in this order by the data shift register unit 101 in synchronism with respective clock pulses that are input to the data shift register unit 101, and the data are shifted.
As a result of the sequential shifts in the data shift register unit 101, an integration result for the sampling phases A0 to A63 is output as an output SA0 (output S) at timing of clock edge No. 253 and an integration result for the sampling phases C0 to C63 is output as an output SC0 at timing of clock edge No. 255.
FIG. 5 is a timing chart showing a control signal, output signals TAPD0 to TAPD63 of the data shift register unit 101, and an output S of the cumulative addition unit 104 as a partial integration result of the conventional 1-symbol integration, 4-time-divisional matched filter circuit 100 of FIG. 1 in a case that 1-fold oversampling is set.
Input data having sampling phases A0, A1, A2, A3, A4, A5, A6, A7, . . . are captured in this order by the data shift register unit 101 in synchronism with respective clock pulses that are input to the data shift register unit 101, and the data are shifted.
As a result of the sequential shifts in the data shift register unit 101, an integration result for the sampling phases A0 to A63 is output as an output SA0 (output S) at timing of clock edge No. 253.
FIG. 6 is a timing chart showing how a delay profile as a 1-symbol correlation result is generated from partial integration results (see FIGS. 3-5) when each kind of oversampling is set.
Where 4-fold oversampling is set, a partial integration result SA0 for the sampling phase A, a partial integration result SB0 for the sampling phase B, a partial integration result SC0 for the sampling phase C, and a partial integration result SD0 for the sampling phase D are calculated sequentially in synchronism with respective clock pulses from clock edge No. 1 for the first ¼ symbol (in the head search window) on the basis of which a delay profile is to be generated.
Results SA0-SA63, SB0-SB63, SC0-SC63, and SD0-SD63 that are output sequentially in the above manner are partial integration results of the first ¼ symbol on the basis of which a delay profile is to be generated, and hence are stored at addresses 0-255 of the RAM unit 105.
Results SA64-SA127, SB64-SB127, SC64-SC127, and SD64-SD127 that are output from clock edge No. 257 are partial integration results of the second ¼ symbol on the basis of which a delay profile is to be generated. Therefore, the partial integration results SA0-SA63, SB0-SB63, SC0-SC63, and SD0-SD63 of the first ¼ symbol that are stored at addresses 0-255 of the RAM unit 105 are read out, and partial integration results (SA0+SA64) to (SA63+SA127), (SB0+SB64) to (SB63+SB127), (SC0+SC64) to (SC63+SC127), and (SD0+SD64) to (SD63+SD127) of the first 2/4 symbol on the basis of which a delay profile is to be generated are calculated and stored at the same addresses of the RAM unit 105.
Results SA128-SA191, SB128-SB191, SC128-SC191, and SD128-SD191 that are output from clock edge No. 513 are partial integration results of the third ¼ symbol on the basis of which a delay profile is to be generated. Therefore, the partial integration results (SA0+SA64) to (SA63+SA127), (SB0+SB64) to (SB63+SB127), (SC0+SC64) to (SC63+SC127), and (SD0+SD64) to (SD63+SD127) of the first 2/4 symbol that are stored at addresses 0-255 of the RAM unit 105 are read out, and partial integration results (SA0+SA64+SA128) to (SA63+SA127+SA191), (SB0+SB64+SB128) to (SB63+SB127+SB191), (SC0+SC64+SC128) to (SC63+SC127+SC191), and (SD0+SD64+SD128) to (SD63+SD127+SD191) of the first ¾ symbol on the basis of which a delay profile is to be generated are calculated and stored at the same addresses of the RAM unit 105.
Results SA192-SA255, SB192-SB255, SC192-SC255, and SD192-SD255 that are output from clock edge No. 769 are partial integration results of the fourth ¼ symbol on the basis of which a delay profile is to be generated. Therefore, the partial integration results (SA0+SA64+SA128) to (SA63+SA127+SA191), (SB0+SB64+SB128) to (SB63+SB127+SB191), (SC0+SC64+SC128) to (SC63+SC127+SC191), and (SD0+SD64+SD128) to (SD63+SD127+SD191) of the first ¾ symbol that are stored at addresses 0-255 of the RAM unit 105 are read out, and partial integration results (SA0+SA64+SA128+SA192) to (SA63+SA127+SA191+SA255), (SB0+SB64+SB128+SB192) to (SB63+SB127+SB191+SB255), (SC0+SC64+SC128+SC192) to (SC63+SC127+SC191+SC255), and (SD0+SD64+SD128+SD192) to (SD63+SD127+SD191+SD255) of the one entire symbol to become a delay profile are calculated and output as a 1-symbol correlation result (i.e., delay profile).
Where 2-fold oversampling is set, a partial integration result SA0 for the sampling phase A is calculated at clock edge No. 1 and a partial integration result SC0 for the sampling phase C is calculated with a delay of 2 clock cycles, for the first ¼ symbol (in the head search window) on the basis of which a delay profile is to be generated.
Results SA0-SA63 and SC0-SC63 that are output sequentially in the above manner are partial integration results of the first ¼ symbol on the basis of which a delay profile is to be generated, and hence are stored at addresses 0-127 of the RAM unit 105.
Results SA64-SA127 and SC64-SC127 that are output from clock edge No. 257 are partial integration results of the second ¼ symbol on the basis of which a delay profile is to be generated. Therefore, the partial integration results SA0-SA63 and SC0-SC63 of the first ¼ symbol that are stored at addresses 0-127 of the RAM unit 105 are read out, and partial integration results (SA0+SA64) to (SA63+SA127) and (SC0+SC64) to (SC63+SC127) of the first 2/4 symbol on the basis of which a delay profile is to be generated are calculated and stored at the same addresses of the RAM unit 105.
Results SA128-SA191 and SC128-SC191 that are output from clock edge No. 513 are partial integration results of the third ¼ symbol on the basis of which a delay profile is to be generated. Therefore, the partial integration results (SA0+SA64) to (SA63+SA127) and (SC0+SC64) to (SC63+SC127) of the first 2/4 symbol that are stored at addresses 0-127 of the RAM unit 105 are read out, and partial integration results (SA0+SA64+SA128) to (SA63+SA127+SA191) and (SC0+SC64+SC128) to (SC63+SC127+SC191) of the first ¾ symbol on the basis of which a delay profile is to be generated are calculated and stored at the same addresses of the RAM unit 105.
Results SA192-SA255 and SC192-SC255 that are output from clock edge No. 769 are partial integration results of the fourth ¼ symbol on the basis of which a delay profile is to be generated. Therefore, the partial integration results (SA0+SA64+SA128) to (SA63+SA127+SA191) and (SC0+SC64+SC128) to (SC63+SC127+SC191) of the first ¾ symbol that are stored at addresses 0-127 of the RAM unit 105 are read out, and partial integration results (SA0+SA64+SA128+SA192) to (SA63+SA127+SA191+SA255) and (SC0+SC64+SC128+SC192) to (SC63+SC127+SC191+SC255) of the one entire symbol to become a delay profile are calculated and output as a 1-symbol correlation result (i.e., delay profile).
Where 1-fold oversampling is set, a partial integration result SA0 of data having the sampling phase A is calculated at clock edge No. 1 for the first ¼ symbol (in the head search window) on the basis of which a delay profile is to be generated.
Results SA0-SA63 that are output sequentially in the above manner are partial integration results of the first ¼ symbol on the basis of which a delay profile is to be generated, and hence are stored at addresses 0-63 of the RAM unit 105.
Results SA64-SA127 that are output from clock edge No. 257 are partial integration results of the second ¼ symbol on the basis of which a delay profile is to be generated. Therefore, the partial integration results SA0-SA63 of the first ¼ symbol that are stored at addresses 0-63 of the RAM unit 105 are read out, and partial integration results (SA0+SA64) to (SA63+SA127) of the first 2/4 symbol on the basis of which a delay profile is to be generated are calculated and stored at the same addresses of the RAM unit 105.
Results SA128-SA191 that are output from clock edge No. 513 are partial integration results of the third ¼ symbol on the basis of which a delay profile is to be generated. Therefore, the partial integration results (SA0+SA64) to (SA63+SA127) of the first 2/4 symbol that are stored at addresses 0-63 of the RAM unit 105 are read out, and partial integration results (SA0+SA64+SA128) to (SA63+SA127+SA191) of the first ¾ symbol on the basis of which a delay profile is to be generated are calculated and stored at the same addresses of the RAM unit 105.
Results SA192-SA255 that are output from clock edge No. 769 are partial integration results of the fourth ¼ symbol on the basis of which a delay profile is to be generated. Therefore, the partial integration results (SA0+SA64+SA128) to (SA63+SA127+SA191) of the first ¾ symbol that are stored at addresses 0-63 of the RAM unit 105 are read out, and partial integration results (SA0+SA64+SA128+SA192) to (SA63+SA127+SA191+SA255) of the one entire symbol to become a delay profile are calculated and output as a 1-symbol correlation result (i.e., delay profile).
The point to which attention should be paid in the above processing is that in every kind of oversampling setting the length of reception data that can be captured by the data shift register unit 101 of the matched filter circuit 100 is fixed to the ¼-symbol length.
In the above conventional matched filter circuit 100, to switch the sampling accuracy of data to be received, as the oversampling setting number is switched in order of 4, 2, and 1 the operation speed of the matched filter circuit 100 is lowered so as to conform to the rate of reception data.
More specifically, let H represent an operation speed at which the matched filter circuit 100 needs to operate when 4-fold oversampling is set; then, the matched filter circuit 100 needs to operate at operation speeds H/2 and H/4 when 2-fold oversampling and 1-fold oversampling are set, respectively.
Further, in conventional 1-symbol integration time-divisional matched filter circuits, the search window width decreases at the same rate as the number of taps decreases, which is in contrast to matched filter circuits in which 1-symbol integration is performed at once.